The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2011

Filed:

Jun. 28, 2010
Applicants:

Weiguang LU, San Jose, CA (US);

Eric E. Edwards, Albuquerque, NM (US);

Paul-hugo Lamarche, San Jose, CA (US);

Steven P. Young, Boulder, CO (US);

Brian C. Gaide, Glassboro, NJ (US);

Joe Eddie Leyba, Ii, Albuquerque, NM (US);

Inventors:

Weiguang Lu, San Jose, CA (US);

Eric E. Edwards, Albuquerque, NM (US);

Paul-Hugo Lamarche, San Jose, CA (US);

Steven P. Young, Boulder, CO (US);

Brian C. Gaide, Glassboro, NJ (US);

Joe Eddie Leyba, II, Albuquerque, NM (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.


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