Integration scheme for strained source/drain cmos using oxide hard mask

Abstract

A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate, the first well region and the second well region, and forming a polysilicon gate layer (e.g., doped polysilicon) overlying the dielectric layer. The polysilicon gate layer is overlying a first channel region in the first well region and a second channel region in the second well region. The method includes forming a hard mask (e.g., silicon dioxide) overlying the polysilicon gate layer and patterning the polysilicon gate layer and the hard mask layer to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region. Next, the method separately forms strained regions in the first and second well regions.