Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices

Abstract

An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed.