The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

May. 25, 2004
Applicants:

Nozomu Matsuzaki, Kokubunji, JP;

Tetsuya Ishimaru, Kokubunji, JP;

Makoto Mizuno, Setagaya, JP;

Takashi Hashimoto, Iruma, JP;

Inventors:

Nozomu Matsuzaki, Kokubunji, JP;

Tetsuya Ishimaru, Kokubunji, JP;

Makoto Mizuno, Setagaya, JP;

Takashi Hashimoto, Iruma, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 7/00 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.


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