The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Dec. 28, 2009
Applicants:

Seung-eon Ahn, Suwon-si, KR;

Ho-jung Kim, Suwon-si, KR;

Chul-woo Park, Yongin-si, KR;

Sang-beom Kang, Hwaseong-si, KR;

Hyun-ho Choi, Suwon-si, KR;

Inventors:

Seung-eon Ahn, Suwon-si, KR;

Ho-jung Kim, Suwon-si, KR;

Chul-woo Park, Yongin-si, KR;

Sang-beom Kang, Hwaseong-si, KR;

Hyun-ho Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.


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