The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Nov. 21, 2007
Applicants:

Yu-min Lin, Hsin-Chu, TW;

Hsin-li Chen, Hsin-Chu, TW;

Feng-yuan Gan, Hsin-Chu, TW;

Inventors:

Yu-Min Lin, Hsin-Chu, TW;

Hsin-Li Chen, Hsin-Chu, TW;

Feng-Yuan Gan, Hsin-Chu, TW;

Assignee:

AU Optronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/038 (2006.01); G09G 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.


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