The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2011
Filed:
May. 21, 2008
Kenneth R. Rhyner, Rockwall, TX (US);
Kevin Lyne, Fairview, TX (US);
David G. Wontor, Dublin, CA (US);
Peter R. Harper, Lucas, TX (US);
Kenneth R. Rhyner, Rockwall, TX (US);
Kevin Lyne, Fairview, TX (US);
David G. Wontor, Dublin, CA (US);
Peter R. Harper, Lucas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor flip-chip ball grid array package () with one-metal-layered substrate. The sites () of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (), when the sites can be routed for metal plating (). The space to place a maximum number () of signal routing traces is opened up by interrupting the periodicity of the site array from the edge () of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.