The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Jul. 14, 2009
Applicants:

Kezhakkedath R. Udayakumar, Dallas, TX (US);

Lindsey H. Hall, Plano, TX (US);

Francis G. Celii, Dallas, TX (US);

Scott R. Summerfelt, Garland, TX (US);

Inventors:

Kezhakkedath R. Udayakumar, Dallas, TX (US);

Lindsey H. Hall, Plano, TX (US);

Francis G. Celii, Dallas, TX (US);

Scott R. Summerfelt, Garland, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.


Find Patent Forward Citations

Udayakumar, Kezhakkedath. (2011). Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean (U.S. Patent No. 8053252). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8053252

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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