The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Oct. 12, 2009
Thaddeus Clay Mccracken, Tigard, OR (US);
Jong-chang Lee, Macungie, PA (US);
Ping-chih Wu, Cupertino, CA (US);
Cecile Nghiem, Union City, CA (US);
Kit Lam Cheong, Palo Alto, CA (US);
Patrick John Eichenseer, Austin, TX (US);
Thaddeus Clay McCracken, Tigard, OR (US);
Jong-Chang Lee, Macungie, PA (US);
Ping-Chih Wu, Cupertino, CA (US);
Cecile Nghiem, Union City, CA (US);
Kit Lam Cheong, Palo Alto, CA (US);
Patrick John Eichenseer, Austin, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.