The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Jul. 01, 2008
Akira Yamauchi, Yokohama, JP;
Hiroyuki Tsurumi, Fujisawa, JP;
Akira Yamauchi, Yokohama, JP;
Hiroyuki Tsurumi, Fujisawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
An n-channel integrated circuit device (n is an integer of 1 or greater) for muting an audio signal includes a control circuit configured to generate a control signal and a delayed control signal, a charging and discharging circuit configured to charge and discharge a time constant control terminal according to the control signal and the delayed control signal, an N-th voltage-to-current converting circuit (N is an integer from 1 to n) configured to generate a (2N−1)-th current corresponding to a voltage on the time constant control terminal and a (2N)-th current corresponding to an intermediate voltage, a (2N−1)-th mirror circuit configured to copy the (2N−1)-th current to generate (4N−3)-th and (4N−2)-th intermediate currents, a (2N)-th mirror circuit configured to copy the (2N)-th current to generate (4N−1)-th and (4N)-th intermediate currents, a (2N−1)-th selecting and combining circuit configured to combine a (2N−1)-th mute control current using the (4N−3)-th intermediate current and the (4N−1)-th intermediate current, and a (2N)-th selecting and combining circuit configured to combine a (2N)-th mute control current using the (4N−2)-th intermediate current and the (4N)-th intermediate current.