The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2011

Filed:

Dec. 02, 2009
Applicants:

Hee Chai Kang, Namwon-si, KR;

Kyeong Ho Ryu, Seoul, KR;

Seong Ook Jung, Goyang-si, KR;

Won Lee, Gunpo-si, KR;

Dong Hwan Lee, Seongnam-si, KR;

Alex Joo, Yongin-si, KR;

Jong-ryun Choi, Hwasung-si, KR;

Inventors:

Hee Chai Kang, Namwon-si, KR;

Kyeong Ho Ryu, Seoul, KR;

Seong Ook Jung, Goyang-si, KR;

Won Lee, Gunpo-si, KR;

Dong Hwan Lee, Seongnam-si, KR;

Alex Joo, Yongin-si, KR;

Jong-Ryun Choi, Hwasung-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.


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