The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8049511 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 01, 2011

Filed:

Jun. 20, 2008
Applicants:

LI Xiao, Shenzhen, CN;

I-hsien Chiang, Taoyuan, TW;

Chih-yi Tu, Taoyuan, TW;

Inventors:

Li Xiao, Shenzhen, CN;

I-Hsien Chiang, Taoyuan, TW;

Chih-Yi Tu, Taoyuan, TW;

Assignees:

FuKui Precision Component (Shenzhen) Co., Ltd., Shenzhen, Guangdong Province, CN;

Zhen Ding Technology Co., Ltd., Tayuan, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of detecting faulty via holes of a printed circuit board. The printed circuit board including a number of electric trace segments. The method includes steps of: providing a testing system, the testing system comprising a processor, a storing means and a resistance measuring device, the storing means for storing a function Y=f(X) wherein X represents a reference resistance associated with a given electric trace segment, Yrepresents a minimum threshold value; measuring a resistance of an electric trace segment of a to-be-tested printed circuit board using the resistance measuring device, a to-be-tested via hole located on the electric trace segment; and judging whether the to-be-tested via hole is a faulty via hole according to the following criteria: if |Xa−X|≧Y, the to-be-tested via hole is a faulty via hole, and if |Xa−X|<Y, the to-be-tested via hole is an acceptable via hole, wherein Xa represents the measured resistance of the given electric trace segment counterpart of the to-be-tested printed circuit board.


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