The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
May. 25, 2008
Applicants:
Haruka Shimizu, Kokubunji, JP;
Hidekatsu Onose, Hitachi, JP;
Inventors:
Haruka Shimizu, Kokubunji, JP;
Hidekatsu Onose, Hitachi, JP;
Assignee:
Renesas Electronics Corporation, Kawasaki-shi, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
Abstract
A junction FET having a large gate noise margin is provided. The junction FET comprises an nlayer forming a drift region of the junction FET formed over a main surface of an nsubstrate made of silicon carbide, a player forming a gate region formed in contact with the nlayer forming the drift region and a gate electrode provided in an upper layer of the nsubstrate. The junction FET further incorporates pn diodes formed over the main surface of the nsubstrate and electrically connecting the player forming the gate region and the gate electrode.