The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2011

Filed:

Jul. 09, 2007
Applicants:

Ta-te Chou, Taipei, TW;

Xiong-jie Zhang, Tianjin, CN;

Xian LI, Tianjin, CN;

Hai Fu, Tianjin, CN;

Yong-qi Tian, Tianjin, CN;

Inventors:

Ta-Te Chou, Taipei, TW;

Xiong-Jie Zhang, Tianjin, CN;

Xian Li, Tianjin, CN;

Hai Fu, Tianjin, CN;

Yong-Qi Tian, Tianjin, CN;

Assignee:

Vishay General Semiconductor LLC, Hauppauge, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.


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