The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2011

Filed:

Mar. 25, 2010
Applicants:

Brian K. Kirkpatrick, Allen, TX (US);

Deborah J. Riley, Murphy, TX (US);

Inventors:

Brian K. Kirkpatrick, Allen, TX (US);

Deborah J. Riley, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.


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