The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2011
Filed:
Jan. 14, 2010
Yi MA, Santa Clara, CA (US);
Shreyas S. Kher, Campbell, CA (US);
Khaled Ahmed, Anaheim, CA (US);
Tejal Goyani, Sunnyvale, CA (US);
Maitreyee Mahajani, Saratoga, CA (US);
Jallepally Ravi, Santa Clara, CA (US);
Yi-chiau Huang, Fremont, CA (US);
Yi Ma, Santa Clara, CA (US);
Shreyas S. Kher, Campbell, CA (US);
Khaled Ahmed, Anaheim, CA (US);
Tejal Goyani, Sunnyvale, CA (US);
Maitreyee Mahajani, Saratoga, CA (US);
Jallepally Ravi, Santa Clara, CA (US);
Yi-Chiau Huang, Fremont, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.