The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2011
Filed:
Aug. 23, 2009
Hiroharu Shimizu, Tokyo, JP;
Masakazu Nishibori, Tokyo, JP;
Toshihiko Ochiai, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.