The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
May. 06, 2008
Payman Zarkesh-ha, Albuquerque, NM (US);
Christopher L. Hamlin, Los Gatos, CA (US);
Ashok K. Kapoor, Palo Alto, CA (US);
James S. Koford, Monterey, CA (US);
Madhukar B. Vora, Los Gatos, CA (US);
Payman Zarkesh-Ha, Albuquerque, NM (US);
Christopher L. Hamlin, Los Gatos, CA (US);
Ashok K. Kapoor, Palo Alto, CA (US);
James S. Koford, Monterey, CA (US);
Madhukar B. Vora, Los Gatos, CA (US);
SuVolta, Inc., Los Gatos, CA (US);
Abstract
A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.