The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
Oct. 23, 2007
James A. Culp, Newburgh, NY (US);
Paul Chang, Mahopac, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Praveen Elakkumanan, White Plains, NY (US);
Jason Hibbeler, Williston, VT (US);
Anda C. Mocuta, Lagrangeville, NY (US);
James A. Culp, Newburgh, NY (US);
Paul Chang, Mahopac, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Praveen Elakkumanan, White Plains, NY (US);
Jason Hibbeler, Williston, VT (US);
Anda C. Mocuta, Lagrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.