The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2011

Filed:

Apr. 21, 2009
Applicants:

Sunny Wu, Zhudong Town, TW;

Chih-sheng Shih, Jhubei, TW;

Andy Tsen, Chung-Ho, TW;

JO Fei Wang, Hsin-Chu, TW;

Jong-i Mou, Hsinpu Township, Hsinchu County, TW;

Hsin Kuan, Hsinchu, TW;

Inventors:

Sunny Wu, Zhudong Town, TW;

Chih-Sheng Shih, Jhubei, TW;

Andy Tsen, Chung-Ho, TW;

Jo Fei Wang, Hsin-Chu, TW;

Jong-I Mou, Hsinpu Township, Hsinchu County, TW;

Hsin Kuan, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/00 (2006.01); G06F 19/00 (2006.01); G06F 17/00 (2006.01); G06Q 10/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.


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