The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2011

Filed:

Jan. 13, 2009
Applicants:

Yiran Chen, Eden Prairie, MN (US);

Daniel S. Reed, Maple Plain, MN (US);

Yong LU, Edina, MN (US);

Harry Hongyue Liu, Maple Grove, MN (US);

Hai LI, Eden Prairie, MN (US);

Rod V. Bowman, Bloomington, MN (US);

Inventors:

Yiran Chen, Eden Prairie, MN (US);

Daniel S. Reed, Maple Plain, MN (US);

Yong Lu, Edina, MN (US);

Harry Hongyue Liu, Maple Grove, MN (US);

Hai Li, Eden Prairie, MN (US);

Rod V. Bowman, Bloomington, MN (US);

Assignee:

Seagate Technology LLC, Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.


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