The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
Jun. 28, 2007
Kyoung-seok Kim, Seoul, KR;
Kong-soo Lee, Hwaseong-si, KR;
Sang-jin Park, Seongnam-si, KR;
Sung-kwan Kang, Seoul, KR;
Ko-eun Lee, Suwon-si, KR;
Kyoung-Seok Kim, Seoul, KR;
Kong-Soo Lee, Hwaseong-si, KR;
Sang-Jin Park, Seongnam-si, KR;
Sung-Kwan Kang, Seoul, KR;
Ko-Eun Lee, Suwon-si, KR;
Abstract
The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.