The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
May. 09, 2008
Hyeoung-won Seo, Yongin-si, KR;
Jae-man Yoon, Seoul, KR;
Kang-yoon Lee, Seongnam-si, KR;
Dong-gun Park, Seongnam-si, KR;
Bong-soo Kim, Seongnam-si, KR;
Seong-goo Kim, Seoul, KR;
Hyeoung-won Seo, Yongin-si, KR;
Jae-man Yoon, Seoul, KR;
Kang-yoon Lee, Seongnam-si, KR;
Dong-gun Park, Seongnam-si, KR;
Bong-soo Kim, Seongnam-si, KR;
Seong-goo Kim, Seoul, KR;
Abstract
In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.