The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8039400 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 18, 2011

Filed:

Apr. 06, 2009
Applicants:

Frank Koschinsky, Radebeul, DE;

Matthias Lehr, Dresden, DE;

Holger Schuehrer, Dresden, DE;

Inventors:

Frank Koschinsky, Radebeul, DE;

Matthias Lehr, Dresden, DE;

Holger Schuehrer, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.


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Koschinsky, Frank. (2011). Reducing contamination of semiconductor substrates during beol processing by performing a deposition/etch cycle during barrier deposition (U.S. Patent No. 8039400). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8039400

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