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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8037394 B1

PDFFull Text
Date of Patent:
Oct. 11, 2011

Filed:

Jun. 29, 2007

Techniques for generating bit reliability information in a post-processor using an error correction constraint

Applicants:

Ivana Djurdjevic, San Jose, CA (US);

Bruce Alexander Wilson, San Jose, CA (US);

Mario Blaum, San Jose, CA (US);

Richard Leo Galbraith, Rochester, MN (US);

Ksenija Lakovic, Menlo Park, CA (US);

Yuan Xing Lee, San Jose, CA (US);

Zongwang LI, San Jose, CA (US);

Travis Roger Oenning, Rochester, MN (US);

Inventors:

Ivana Djurdjevic, San Jose, CA (US);

Bruce Alexander Wilson, San Jose, CA (US);

Mario Blaum, San Jose, CA (US);

Richard Leo Galbraith, Rochester, MN (US);

Ksenija Lakovic, Menlo Park, CA (US);

Yuan Xing Lee, San Jose, CA (US);

Zongwang Li, San Jose, CA (US);

Travis Roger Oenning, Rochester, MN (US);

Assignee:

Hitachi Global Storage Technologies Netherlands, B.V., Amsterdam, NL;

Attorney:

Steven J. Cahill

Primary Examiner:

Stephen Baker

Int. Cl.
CPC ...
H03M 13/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.

Find Patent Forward Citations

Djurdjevic, Ivana. (2011). Techniques for generating bit reliability information in a post-processor using an error correction constraint (U.S. Patent No. 8037394). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8037394

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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