The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8035232 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 11, 2011

Filed:

May. 08, 2009
Applicants:

Takeshi Harada, Shiga, JP;

Junichi Shibata, Hyogo, JP;

Akira Ueki, Osaka, JP;

Inventors:

Takeshi Harada, Shiga, JP;

Junichi Shibata, Hyogo, JP;

Akira Ueki, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating film. A liner insulating film is formed on the upper surfaces of the interlayer insulating film and lower-level interconnects. An interlayer insulating film is formed on the upper surface of the liner insulating film. Upper-level interconnects are formed in the interlayer insulating film. The lower-level interconnects and the upper-level interconnects are connected with each other through vias. Parts of the liner insulating film formed in via-adjacent regions have a greater thickness than a part thereof formed outside the via-adjacent regions.


Find Patent Forward Citations

Harada, Takeshi. (2011). Semiconductor device including interconnects, vias connecting the interconnects and greater thickness of the liner film adjacent the vias (U.S. Patent No. 8035232). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8035232

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