The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8035225 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 11, 2011

Filed:

Dec. 28, 2005
Applicants:

Kojiro Nakamura, Osaka, JP;

Hidenobu Nishikawa, Nara, JP;

Kentaro Kumazawa, Osaka, JP;

Inventors:

Kojiro Nakamura, Osaka, JP;

Hidenobu Nishikawa, Nara, JP;

Kentaro Kumazawa, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly including a plurality of upper side pads () provided on a substrate upper surface (); a plurality of lower side pads () provided on a substrate lower surface () corresponding to the upper side pads () across the substrate (), respectively; a first semiconductor chip () having first bumps () joined to the upper side pads (), respectively; and a second semiconductor chip () having second bumps () joined to the lower side pads (), respectively.


Find Patent Forward Citations

Nakamura, Kojiro. (2011). Semiconductor chip assembly and fabrication method therefor (U.S. Patent No. 8035225). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8035225

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