The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2011

Filed:

Feb. 25, 2010
Applicants:

Huiming Bu, Ossining, NY (US);

Eduard A. Cartier, New York, NY (US);

Bruce B. Doris, Brewster, NY (US);

Young-hee Kim, Mohegan Lake, NY (US);

Barry Linder, Hastings-on-Hudson, NY (US);

Vijay Narayanan, New York, NY (US);

Vamsi K. Paruchuri, Albany, NY (US);

Michelle L. Steen, Danbury, CT (US);

Inventors:

Huiming Bu, Ossining, NY (US);

Eduard A. Cartier, New York, NY (US);

Bruce B. Doris, Brewster, NY (US);

Young-Hee Kim, Mohegan Lake, NY (US);

Barry Linder, Hastings-on-Hudson, NY (US);

Vijay Narayanan, New York, NY (US);

Vamsi K. Paruchuri, Albany, NY (US);

Michelle L. Steen, Danbury, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.


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