The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2011
Filed:
Oct. 31, 2008
Hiroshi Ishida, Tokyo, JP;
Atsushi Maeda, Tokyo, JP;
Minoru Abiko, Tokyo, JP;
Takehiko Kijima, Tokyo, JP;
Takashi Takeuchi, Tokyo, JP;
Shoji Yoshida, Tokyo, JP;
Natsuo Yamaguchi, Tokyo, JP;
Yasuhiro Kimura, Tokyo, JP;
Tetsuya Uchida, Tokyo, JP;
Norio Ishitsuka, Tokyo, JP;
Hiroshi Ishida, Tokyo, JP;
Atsushi Maeda, Tokyo, JP;
Minoru Abiko, Tokyo, JP;
Takehiko Kijima, Tokyo, JP;
Takashi Takeuchi, Tokyo, JP;
Shoji Yoshida, Tokyo, JP;
Natsuo Yamaguchi, Tokyo, JP;
Yasuhiro Kimura, Tokyo, JP;
Tetsuya Uchida, Tokyo, JP;
Norio Ishitsuka, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG.. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.