The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2011

Filed:

Nov. 01, 2007
Applicants:

Naomu Kitano, Ichikawa, JP;

Takashi Minami, Fuchu, JP;

Motomu Kosuda, Machida, JP;

Heiji Watanabe, Suita, JP;

Inventors:

Naomu Kitano, Ichikawa, JP;

Takashi Minami, Fuchu, JP;

Motomu Kosuda, Machida, JP;

Heiji Watanabe, Suita, JP;

Assignee:

Canon Anelva Corporation, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film is formed by sputtering a Hf metal film on a SiOfilm (or a SiON film) on a Si wafer. A TiOfilm is formed by sputtering a Ti metal film on the HfSiO film and subjecting the Ti metal film to a thermal oxidation treatment. A TiN metal film is deposited on the TiOfilm. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO/HfSiO/SiO/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis <20 mV.


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