Transistor structure having reduced input capacitance

Abstract

A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (). The conductive shield layer () is isolated from the gate of the transistor by more than one dielectric layer (, and) to reduce input capacitance. The pedestal region includes an air gap region () to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer ().