The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2011

Filed:

Nov. 20, 2007
Applicants:

Jeffrey Peter Gambino, Westford, VT (US);

Benjamin Thomas Voegeli, Burlington, VT (US);

Steven Howard Voldman, South Burlington, VT (US);

Michael Joseph Zierak, Essex Junction, VT (US);

Inventors:

Jeffrey Peter Gambino, Westford, VT (US);

Benjamin Thomas Voegeli, Burlington, VT (US);

Steven Howard Voldman, South Burlington, VT (US);

Michael Joseph Zierak, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/119 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.


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