The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2011
Filed:
Apr. 30, 2008
Masato Yonezawa, Tokyo, JP;
Kimikazu Hazumi, Tokyo, JP;
Akihiro Takami, Tokyo, JP;
Hiroaki Morikawa, Tokyo, JP;
Kunihiko Nishimura, Tokyo, JP;
Masato Yonezawa, Tokyo, JP;
Kimikazu Hazumi, Tokyo, JP;
Akihiro Takami, Tokyo, JP;
Hiroaki Morikawa, Tokyo, JP;
Kunihiko Nishimura, Tokyo, JP;
Mitsubishi Electric Corporation, Chiyoda-Ku, Tokyo, JP;
Abstract
The manufacturing method includes: forming a P-type silicon substrate and a high-concentration N-type diffusion layer, in which an N-type impurity is diffused in a first concentration, on an entire surface at a light-incident surface side; forming an etching resistance film on the high-concentration N-type diffusion layer and forming fine pores at a predetermined position within a recess forming regions on the etching resistance film; forming recesses by etching the silicon substrate around a forming position of the fine pores, so as not to leave the high-concentration N-type diffusion layer within the recess forming region; forming the low-concentration N-type diffusion layer, in which an N-type impurity is diffused in a second concentration that is lower than the first concentration, on a surface on which the recesses are formed; and forming a grid electrode in an electrode forming region at a light-incident surface side of the silicon substrate.