The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2011

Filed:

Sep. 05, 2007
Applicants:

Masahiro Wada, Tokyo, JP;

Hiroyuki Tanaka, Tokyo, JP;

Hiroshi Hirose, Tokyo, JP;

Teppei Itoh, Tokyo, JP;

Kenya Tachibana, Tokyo, JP;

Inventors:

Masahiro Wada, Tokyo, JP;

Hiroyuki Tanaka, Tokyo, JP;

Hiroshi Hirose, Tokyo, JP;

Teppei Itoh, Tokyo, JP;

Kenya Tachibana, Tokyo, JP;

Assignee:

Sumitomo Bakelight Co., Ltd., Shinagawa-Ku, Tokyo, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/18 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes.


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