The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2011
Filed:
Nov. 13, 2008
Shun-jang Liao, Pingjhen, TW;
Sheng-chen Chung, Jhubei, TW;
Kong-beng Thei, Hsin-Chu, TW;
Harry Chuang, Hsin-Chu, TW;
Shun-Jang Liao, Pingjhen, TW;
Sheng-Chen Chung, Jhubei, TW;
Kong-Beng Thei, Hsin-Chu, TW;
Harry Chuang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.