The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2011
Filed:
May. 13, 2009
Ra-min Tain, Taipei County, TW;
Yu-lin Chao, Hsinchu, TW;
Shu-jung Yang, Tainan County, TW;
Rong-chang Fang, Hsinchu, TW;
Wei LI, Hsinchu, TW;
Chih-yuan Cheng, Taipei County, TW;
Ming-che Hsieh, Kaohsiung, TW;
Ra-Min Tain, Taipei County, TW;
Yu-Lin Chao, Hsinchu, TW;
Shu-Jung Yang, Tainan County, TW;
Rong-Chang Fang, Hsinchu, TW;
Wei Li, Hsinchu, TW;
Chih-Yuan Cheng, Taipei County, TW;
Ming-Che Hsieh, Kaohsiung, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.