The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2011
Filed:
Apr. 03, 2009
Myung-sam Kang, Daejeon, KR;
Chang-sup Ryu, Yongin-si, KR;
Jung-hyun Park, Cheongju-si, KR;
Hoe-ku Jung, Daejeon, KR;
Ji-eun Kim, Gwangmyeong-si, KR;
Myung-Sam Kang, Daejeon, KR;
Chang-Sup Ryu, Yongin-si, KR;
Jung-Hyun Park, Cheongju-si, KR;
Hoe-Ku Jung, Daejeon, KR;
Ji-Eun Kim, Gwangmyeong-si, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.