The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2011
Filed:
Apr. 04, 2007
Yongjun Zheng, Union City, CA (US);
David Mark, San Jose, CA (US);
Joe W. Zhao, San Jose, CA (US);
Felino Encarnacion Pagaduan, San Jose, CA (US);
Yongjun Zheng, Union City, CA (US);
David Mark, San Jose, CA (US);
Joe W. Zhao, San Jose, CA (US);
Felino Encarnacion Pagaduan, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.