The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2011
Filed:
Aug. 17, 2009
Eduard A. Cartier, New York, NY (US);
Matthew W. Copel, Yorktown Heights, NY (US);
Bruce B. Doris, Brewster, NY (US);
Rajarao Jammy, Hopewell Junction, NY (US);
Young-hee Kim, Yorktown Heights, NY (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
Vamsi K. Paruchuri, New York, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
Eduard A. Cartier, New York, NY (US);
Matthew W. Copel, Yorktown Heights, NY (US);
Bruce B. Doris, Brewster, NY (US);
Rajarao Jammy, Hopewell Junction, NY (US);
Young-Hee Kim, Yorktown Heights, NY (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
Vamsi K. Paruchuri, New York, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.