Dll circuit with wide-frequency locking range and error-locking-avoiding function

Abstract

A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the delay period of time of the voltage control delay circuit analogically. In the locking period, the DLL circuit utilizes the delay time of the delay units, which is decided in the evaluation period, along with the voltage control delay circuit, to lock phase of the reference clock signal. In this way, the stability of the delay period of time of the voltage control delay circuit increases.