The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2011
Filed:
Oct. 05, 2009
Richard John Fagerlund, San Jose, CA (US);
James P. Flynn, Palo Alto, CA (US);
Mark Fong, San Jose, CA (US);
David Bruce Isaksen, Mountain View, CA (US);
Richard John Fagerlund, San Jose, CA (US);
James P. Flynn, Palo Alto, CA (US);
Mark Fong, San Jose, CA (US);
David Bruce Isaksen, Mountain View, CA (US);
Wideband Semiconductor, Inc., Mountain View, CA (US);
Abstract
A method for digital clock smoothing is provided. The method comprises: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting FIFO depth B into a programmable look-up table (LUT); (D) obtaining a phase detector error signal; (E) scaling the phase detector error signal to obtain a scaled error factor; (F) adding the scaled error factor to a nominal phase step to obtain a phase update; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from FIFO under control of an output FIFO address control register at the smoothed symbol rate.