The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2011
Filed:
Dec. 14, 2010
Satoru Akiyama, Sagamihara, JP;
Tomonori Sekiguchi, Tama, JP;
Riichiro Takemura, Tokyo, JP;
Hiroaki Nakaya, Kokubunji, JP;
Shinichi Miyatake, Tokyo, JP;
Yuko Watanabe, Tokyo, JP;
Satoru Akiyama, Sagamihara, JP;
Tomonori Sekiguchi, Tama, JP;
Riichiro Takemura, Tokyo, JP;
Hiroaki Nakaya, Kokubunji, JP;
Shinichi Miyatake, Tokyo, JP;
Yuko Watanabe, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.