The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2011

Filed:

Jul. 16, 2009
Applicants:

Hajime Nakabayashi, Nirasaki, JP;

Yasushi Akasaka, Nirasaki, JP;

Tetsuya Shibata, Nirasaki, JP;

Inventors:

Hajime Nakabayashi, Nirasaki, JP;

Yasushi Akasaka, Nirasaki, JP;

Tetsuya Shibata, Nirasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer.


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