The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2011
Filed:
Dec. 27, 2007
Jong-han Shin, Ichon-shi, KR;
Hyung-soon Park, Ichon-shi, KR;
Cheol-hwi Ryu, Ichon-shi, KR;
Jum-yong Park, Ichon-shi, KR;
Sung-jun Kim, Ichon-shi, KR;
Jong-Han Shin, Ichon-shi, KR;
Hyung-Soon Park, Ichon-shi, KR;
Cheol-Hwi Ryu, Ichon-shi, KR;
Jum-Yong Park, Ichon-shi, KR;
Sung-Jun Kim, Ichon-shi, KR;
Hynix Semiconductor Inc., Icheon-si, KR;
Abstract
A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.