The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2011
Filed:
Apr. 27, 2009
Axel Aguado Granados, Rochester, MN (US);
Benjamin Aaron Fox, Rochester, MN (US);
Nathaniel James Gibbs, Rochester, MN (US);
Andrew Benson Maki, Rochester, MN (US);
Trevor Joseph Timpane, Rochester, MN (US);
Axel Aguado Granados, Rochester, MN (US);
Benjamin Aaron Fox, Rochester, MN (US);
Nathaniel James Gibbs, Rochester, MN (US);
Andrew Benson Maki, Rochester, MN (US);
Trevor Joseph Timpane, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectric above the first metal layer. A second layer of silicon dioxide dielectric is deposited and the vertical air gap is sealed. A next trace layer is etched from the second layer of silicon dioxide dielectric and a via opening is etched from the second and first layers of silicon dioxide dielectric. Then metal is deposited into the next trace layer and metal is deposited into the via opening.