The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2011
Filed:
Dec. 30, 2009
Sung-yong Chung, Santa Clara, CA (US);
Zhizheng Liu, San Jose, CA (US);
Yugi Mizuguchi, Santa Clara, CA (US);
Xuguang Alan Wang, Eden Prairie, MN (US);
Yi He, Fremont, CA (US);
Ming Kwan, San Leandro, CA (US);
Darlene Hamilton, Lyle, WA (US);
Sung-chul Lee, Cupertino, CA (US);
Guowei Wang, San Jose, CA (US);
Nancy Leong, Cupertino, CA (US);
Sung-Yong Chung, Santa Clara, CA (US);
Zhizheng Liu, San Jose, CA (US);
Yugi Mizuguchi, Santa Clara, CA (US);
Xuguang Alan Wang, Eden Prairie, MN (US);
Yi He, Fremont, CA (US);
Ming Kwan, San Leandro, CA (US);
Darlene Hamilton, Lyle, WA (US);
Sung-Chul Lee, Cupertino, CA (US);
Guowei Wang, San Jose, CA (US);
Nancy Leong, Cupertino, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.