The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2011
Filed:
Oct. 28, 2009
Sunil Mehta, San Jose, CA (US);
Stewart Logie, Campbell, CA (US);
Steven Fong, Santa Clara, CA (US);
Sunil Mehta, San Jose, CA (US);
Stewart Logie, Campbell, CA (US);
Steven Fong, Santa Clara, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxidized to form a silicon dioxide layer lining the first and second trenches, the layer having a first thickness. A silicon nitride layer is deposited on the silicon dioxide layer in the first and second trenches. The silicon nitride layer is then etched from the first trench but not from the second trench, thereby exposing the silicon layer in the first trench but not the second trench. The exposed silicon dioxide layer in the first trench is oxidized to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second trench. The first and second trenches are then filled with a dielectric material.