Automated multiple voltage/power state design process and chip description system

Abstract

Systems and methods are disclosed herein which compensate for the loss in design information that occurs when the design is represented in traditional functional descriptions. An automated multiple voltage/power state design process includes creating a plurality of design objects; processing a design definition according to the voltage effects design object; and generating a modified design output such that communication between a plurality of design process steps, wherein the plurality of design process steps include a parsing step, a RTL simulation step, a synthesis step, a gate simulation step, formal verification step, and physical design and verification step in accordance with the voltage effects design object. A system for automating a multiple voltage/power state design process includes a design definition module; a parser module, a RTL simulation module, a synthesis module, a gate simulation module, and a formal verification module wherein the automation of a multiple voltage/power state design process is achieved. The system can include a physical design and verification module coupled to the synthesis module.