The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2011
Filed:
Oct. 11, 2010
Naozumi Morino, Tokyo, JP;
Atsushi Hiraiwa, Tokyo, JP;
Kazutoshi Oku, Tokyo, JP;
Toshiaki Ito, Tokyo, JP;
Motoshige Igarashi, Tokyo, JP;
Takayuki Sasaki, Tokyo, JP;
Masao Sugiyama, Tokyo, JP;
Hiroshi Yanagita, Tokyo, JP;
Shinichi Watarai, Tokyo, JP;
Naozumi Morino, Tokyo, JP;
Atsushi Hiraiwa, Tokyo, JP;
Kazutoshi Oku, Tokyo, JP;
Toshiaki Ito, Tokyo, JP;
Motoshige Igarashi, Tokyo, JP;
Takayuki Sasaki, Tokyo, JP;
Masao Sugiyama, Tokyo, JP;
Hiroshi Yanagita, Tokyo, JP;
Shinichi Watarai, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.