The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2011

Filed:

Oct. 12, 2007
Applicants:

Prasun K. Raha, Redwood City, CA (US);

Donald Stark, Palo Alto, CA (US);

Dean Liu, Sunnyvale, CA (US);

Pak Shing Chau, San Jose, CA (US);

Inventors:

Prasun K. Raha, Redwood City, CA (US);

Donald Stark, Palo Alto, CA (US);

Dean Liu, Sunnyvale, CA (US);

Pak Shing Chau, San Jose, CA (US);

Assignees:

Xilinx, Inc., San Jose, CA (US);

NetLogic Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.


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